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Toshiba Corporation and Toshiba America Electronic Components, Inc., (TAEC)*, a committed leader that collaborates with technology companies to create breakthrough designs, today announced that it began shipping samples of its 64-gigabyte (GB) embedded NAND flash memory module equipped with a Universal Flash Storage (UFS) interface. The first in the industry [1], the new module is fully compliant with the JEDEC UFS [2] Ver.1.1 standard [3], and is designed for a wide range of digital consumer products - including smartphones and tablet PCs.
With improved data processing speeds in host chipsets and wider bandwidths for wireless connectivity, demand continues to grow for large density, high-performance memory that supports high resolution video. A proven innovator in this key area, Toshiba is reinforcing its leadership role by being the first in the industry to ship samples with a 64GB UFS module.
Samples are mainly intended for evaluation of the UFS interface and its protocol in host chipsets and by OS vendors. Toshiba will schedule mass production of the 64GB UFS module, as well as other densities in its lineup, according to market demand.
Product
|
Part Number
|
Density
|
Package
|
Sample shipment
|
|
THGLF0G9B8JBAIE
|
64GB
|
169Ball FBGA
12x16x1.2mm
|
January 2013
|
Key Features
- The JEDEC UFS Ver.1.1 compliant interface handles essential functions, including writing block management, error correction and driver software. It simplifies system development, allowing manufacturers to minimize development costs and speed up time to market for new and upgraded products.
- UFS has a serial interface and
scalability in terms of number of lanes and speed [4].
- The new products are sealed in a small FBGA package, 12x16x1.2mm and have a signal layout compliant with JEDECUFS Ver.1.1.
[1]For embedded NAND flash memory modules. Source: Toshiba, as of February 2013.
[2]Universal Flash Storage is a product category for a class of embedded memory products built to the JEDEC UFS standard specification.
[3]JEDEC UFS Ver.1.1 standard has already been published. The Ver.2.0 standard is now under discussion by JEDEC.
[4]JEDEC UFS Ver.2.0 standard will support multiple-lane and interface speed.
Specifications
|
Interface
|
JEDEC UFS Version 1.1 standard
|
|
Power Supply Voltage
|
2.7V to 3.6V (Memory core?
1.70V to 1.95V ?Controller core?
1.10V to 1.30V (UFS I/F signals)
|
|
Number of lanes
|
Downstream 1 lane / Upstream 1 lane
|
|
Interface Speed
|
2.9Gbps/lane
|
|
Temperature range
|
-25degrees to +85degrees Celsius
|
|
Package
|
169Ball 12x16x1.2mm FBGA
|
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